1. Field of the Invention
The present invention relates generally to interrupt controllers. In one aspect, the present invention relates to an interrupt controller that includes context sensitive interrupt prioritization controlled by hardware.
2. Description of the Related Art
In computer systems, an interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution via a context switch, and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Thus, an interrupt provides a mechanism to force software to alter its current execution and perform tasks that “service” the interrupt. For example, if there is incoming valid data on a serial data interface which is to be stored in a buffer, the serial data interface may assert an interrupt which, when serviced, causes the data to be captured and placed in the buffer. In another example, a processor that is in a sleep mode may receive an interrupt from the keyboard which cases the processor to wake up. In many cases, the prioritization of the serving of interrupts is important since many interrupts relate to interrupt sources that have a limited tolerance for delay in being serviced. For example, the data on the serial data interface may only be valid for a limited amount of time, thus requiring it to be captured within that time period. Servicing of interrupts is typically accomplished through the use of software routines which are referred to as interrupt service routines or interrupt handlers.
Conventional computer systems will use an interrupt controller module to receive interrupt requests from multiple interrupt sources. The requests are stored in an interrupt source register having a bit corresponding to each of the interrupt sources, such that the interrupt source register can be read to determine which sources are asserting pending interrupts. An interrupt enable register stores a bit corresponding to each of the potential pending interrupts, thereby enabling individual bit masking of the interrupt source register. By logically combining (e.g., with a logical AND gate) the individual bits of the interrupt source register and the content of the interrupt enable register, the interrupt requests may be effectively masked and stored in an interrupt pending register. Thus, if an interrupt is asserted and is enabled by the mask register, a logical one will be generated for that interrupt in the interrupt pending register. Conversely, if an interrupt is asserted but is not enabled by the mask register, a logical zero will be generated for that interrupt in the interrupt pending register. The contents of the interrupt pending register are used to generate an interrupt signal in response to any pending, enabled interrupts, and that interrupt signal is routed to the central processing unit (CPU). When the CPU detects that the interrupt signal has been asserted, the interrupt pending register can be examined to determine which interrupt service routine should be executed in response.
When there are multiple, enabled interrupts pending in the interrupt pending register, prioritization of the interrupts has been controlled based on the bit location of a particular interrupt in the interrupt pending register. Thus, a first (or most significant) bit position or section in the interrupt pending register is designated for a first (higher) priority, while a second (or less significant) bit position or section in the interrupt pending register is designated for a second (lower) priority. For example, see U.S. Pat. No. 6,574,693 to Alasti et al. In addition, interrupt priority levels have conventionally been controlled by software, which means that any changes in the prioritization of interrupts (which can occur when the system changes mode or context) requires additional time and programming complexity to switch the prioritization by re-writing the interrupt priority registers or the interrupt pending registers, as the case may be. For an example of a software-controlled interrupt handler, see U.S. Pat. No. 5,459,872 to Connell et al.
Accordingly, there is a need for an improved interrupt controller that allows interrupts to be quickly and efficiently prioritized. There is also a need for a high efficiency interrupt prioritization scheme which allows interrupt priorities to be dynamically controlled and adjusted. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.